1. Field of Invention
The present invention relates to a package structure and the fabrication method thereof. More particularly, the present invention relates to a wafer structure and the bumping process for the wafer structure.
2. Description of Related Art
In the semiconductor industry, integrated circuits (ICs) manufacture can be categorized as three major stages: fabrication of the wafers, fabrication of the ICs and packaging of the ICs. Among the wafer level packaging processes, flip chip (FC) packaging technology has been widely used and become the main stream nowadays. Because FC packaging technology can shorten the signal transmission path between the chip and the substrate, FC packaging technology is suitable for packaging high speed devices, for example, micron or millimeter wave-length operating chip. Moreover, FC package technology can reduce the package size of the chip and provide packages in sizes close to the chip size. Hence, FC packaging technology is extensively applied in packages for high performance computers, PCMCIA card, military instruments, personal communication products, watches and liquid crystal displays.
In FC packaging technology, the arrangement of area arrays is mainly employed. The chip (die) having bonding pads disposed on the active surface of the chip is provided, and bumps are formed on the bonding pads of the chip. After flipping over the chip and arrange the active surface of the chip to the substrate, the bumps are electronically and mechanically connected to the contacts of the substrate or the printed circuit board.
FIG. 1 is a cross-sectional view of a conventional bump structure. Referring to FIG. 1, the structure 100 includes a chip 110 and a plurality of bump structures 120 (with only two bumps shown). The chip 110 has an active surface 112, a passivation layer 114 and a plurality of bonding pads 116 (with only two pads shown) on the active surface 112. The bonding pads 116 are exposed by the passivation layer 114, while the passivation layer 114 covers the active surface 112 of the chip 110.
Each of the bump structure 120 includes an under bump metallurgy (UBM) layer 122 and a bump 124. The UBM layer 122 is arranged between the bump 124 and the bonding pad 116, as an interface for connection. The bump 124 can act as an electrical contact of the chip for external connection.
The UBM layer 122 includes an adhesion layer 122a, a barrier layer 122b, and a wetting layer 122c. The adhesion layer 122a can improve adhesion between the bonding pad 116 and the barrier layer 122b. The barrier layer 122b can act as a barrier against diffusion reaction of the bump 124 or the underlying metal. The wetting layer 122c can increase the attachment of the UBM layer 122 to the bumps 124.
However, in the above structure 100, since the peripheral portion of the UBM layer 122 is disposed on the passivation layer 114, the coefficient of thermal expansion (CTE) mismatch between the chip 110 and the bump structure 120 may result in peeling. Especially under high temperature circumstances (such as pre-heating or temperature tests in the module testing process, or under heat produced from IC operation), thermal stress will induce peeling along the interface between the adhesion layer 122a and the passivation layer 114, thus deteriorating the connection between the chip 110 and the bump structure 120. Hence, the performance of the device is degraded and the life of the device is shortened.